This invention relates to a general purpose register (GPR), used in the design of large computers, that provides for the temporary storage of information, and more particularly to a GPR fabricated using very large scale integration (VLSI) of complementary metal oxide semiconductor (CMOS) circuits. More specifically, the present invention relates to a GPR that has two input ports and two output ports and is designed such that two read operations and two write operations, using four independent addresses, with byte changing between the two inputs and also between an input and an output if desired, can be performed during one cycle of operation.
The use of general purpose registers in the design of large computers is common practice. As the name implies, GPR's are designed to be general purpose and a large number of them might he used in a large computer design to provide temporary storage for the computer hardware for data, addresses, instructions, etc., while the computer executes the instructions of a program.
GPR's have a relatively small number of registers, typically equal to some power of two, but generally no more than thirty-two. Each register of a GPR is an independent storage location but all registers have the same word size (a word consists of some defined number of bits). The word size and the speed of the GPR are determined by the particular application.
In its most simple form, a GPR has a single set of address lines that allow any of the registers to be addressed. When addressed, a register can have data written into it or data read from it, as determined by other control signals of the GPR. Only one write operation or one read operation can take place at a time.
A more sophisticated GPR is one that has two sets of address lines, two data input ports and two data output ports. This design allows two registers within the GPR to be addressed at the same time. Data can be read from both or written into both registers during the same cycle. Such operation is desirable since two data words are often required to be applied to an execution unit within the computer. Alterntively, a read operation from one addressed register and a write operation into the other addressed register during the same cycle is also possible. Control signals are used to enable either or both sets of addresses, and the read and write functions, during every operation.
If parity bits are used as part of the word to insure data integrity, the generation of the parity bits to be written and the checking of parity for the word read is performed by logic circuitry external to the GPR.